1. Field of the Invention
The present invention relates to a precharge/discharge nonvolatile memory circuit such as an EPROM loaded in logic products such as a microcomputer.
2. Description of the Related Art
FIG. 13 is a circuit diagram showing an arrangement of a data readout system of a conventional precharge/discharge nonvolatile memory circuit. A row decoder 11 on the read-cell side selects one of plural word lines RW, and a row decoder on the dummy-cell side selects one of plural dummy word lines DW. A plurality of memory cells, that is, read cells 12 are connected at their control gates to the word lines RW. One end of a current path of each of the read cells 12 is connected to its corresponding bit line BR. A selective transistor 13-1 is arranged at the distal end of the bit line BR. The gate of the selective transistor 13-1 is supplied with an output signal of a column decoder 14-1 and therefore the selective transistor 13-1 is controlled by the column decoder 14-1.
A plurality of dummy cells 15 are connected at their control gates to the dummy word lines DW. One end of a current path of each of the dummy cells 15 is connected to its corresponding dummy bit line BD, and a selective transistor 13-2 is arranged at the distal end of the dummy bit line BD. The selective transistor 13-2 is thus controlled by a column decoder 14-2.
A precharge/discharge control circuit 16 supplies a precharge signal PR to the gates of P-channel precharge transistors P1 and P2 and supplies a discharge signal DIS to the gates of N-channel discharge transistors D1 and D2, in response to a clock signal .phi..
The sources of the precharge transistors P1 and P2 are connected to power supplies V.sub.cc. The drain of the precharge transistor P1 is connected to a connection point between the drains of the selective transistors 13-1 through a transfer transistor N1. The drain of the precharge transistor P2 is connected to a connection point between the drains of the selective transistors 13-2 through a transfer transistor N2.
The gates of the transfer transistors N1 and N2 are supplied with an output signal of a bias voltage generator 17 to control these transfer transistors.
The sources of the discharge transistors D1 and D2 are connected to grounds GND. The drain of the discharge transistor D1 is connected to the other end of the current path of the read cell 12, while the drain of the discharge transistor D2 is connected to the other end of the current path of the dummy cell 15.
A flip-flop circuit 18 is arranged to serve as a circuit for outputting readout data, and its one input terminal Vir is a connection point of the drains of the precharge transistor P1 and the transfer transistor N1 and another input terminal Vid is a connection point of the drains of the precharge transistor P2 and the transfer transistor N2. The flip-flop circuit 18 includes two NOR gate circuits 19 and 20. The output of the NOR gate circuit 19 is connected to the input of the NOR gate circuit 20, while the input of the circuit 19 is connected to the output of the circuit 20. Readout data DOUT is supplied from the output of the NOR gate circuit 20. In addition, the flip-flop circuit 18 can be replaced with a circuit having two inverters, an input terminal of one of the inverters being connected to an output terminal of the other inverter, and an output terminal of the former inverter being connected to an input terminal of the latter inverter.
FIG. 14 is a circuit diagram showing a specific arrangement of the precharge/discharge control circuit 16 of the nonvolatile memory circuit shown in FIG. 13. The precharge/discharge control circuit 16 includes an AND circuit 61, a NAND circuit 62, and inverter circuits 63, 64 and 65. The respective signals input to and output from the circuit 16 are represented by the timing chart shown in FIG. 15. MODE 1 and MODE 2 are test mode signals and become high in level when the reliability of the circuit is checked. Therefore, a normal read mode is set when the MODE 1 and MODE 2 are both low in level.
FIGS. 16 and 17 are timing charts showing an operation of the conventional nonvolatile memory circuit shown in FIG. 13. In FIG. 16, a precharge period is sufficiently long. In FIG. 17, the operating frequency of the memory circuit is increased because of its design, and a precharge period is not sufficiently long.
The precharge transistors P1 and P2 are turned on during the precharge period during which the precharge signal PR and discharge signal DIS are low in level, as shown in FIGS. 16 and 17. Thus, potentials Vir and Vid of the input terminals of the flip-flop circuit 18, potential Vbr of the selected bit line BR, potential Vbd of the dummy bit line BD, and potentials Vsr and Vsd of the selected source lines are precharged. A difference is usually set between gm (reciprocal of on-resistance) of the read cell 12 and that of the dummy cell 15 (gm of read cell&gt;gm of dummy cell). During the precharge period, the potentials Vbr and Vbd differ from each other in change in precharge level, and the potentials Vsr and Vsd also differ from each other in change in precharge level. Though the potentials Vbr and Vsr are higher than the potentials Vbd and Vsd, respectively (Vbr&gt;Vbd, Vsr&gt;Vsd), at the beginning of the precharge period, the difference in level between them is gradually reduced.
If the level of the precharge signal PR is changed from low to high, then that of the discharge signal DIS is changed from low to high, a discharge period starts. If there is a gap due to a wiring delay between the precharge signal PR and discharge signal DIS, each node precharged during the precharge period is dynamically held. The operation of the conventional precharge/discharge nonvolatile memory circuit shown in FIG. 13 in which no electrons are injected into a floating gate of the read cell 12, will now be described.
If the precharge period is sufficiently long as shown in FIG. 16, the precharge levels of the potential Vbr and Vvd and those of the potentials Vsr and Vsd are considerably increased so that Vbr is equal to Vbd and Vsr is equal to Vsd, the precharge period ends, and these potentials are dynamically held. In this case, no charge share occurs in the potentials. When the discharge period starts, a difference in gm between the read cell 12 and the dummy cell 15 is caused, and the input terminal Vir of the flip-flop circuit 18 inevitably reaches a sense level earlier than the input terminal Vid thereof. Consequently, normal readout data DOUT can be output from the flip-flop circuit 18.
If the precharge period is not sufficiently long, as shown in FIG. 17, the precharge period is changed to the discharge period with the precharge levels of the potentials Vbr and Vbd and those of the potentials Vsr and Vsd in an unbalanced state.
Since the capacity of the source line is relatively large, charge is shared with the source line, bit line, and input terminals of the flip-flop circuit, and thus the level of the input terminals is lowered. Since Vbr&gt;Vbd on the bit line and Vsr&gt;Vsd on the source line, Vir&gt;Vid at the input terminals of the flip-flop circuit. Therefore, the level of the input terminals of the flip-flop circuit 18 is decreased to the sense level of the flip-flop circuit 18 with Vir higher than Vid (Vir&gt;Vid) before Vid becomes higher than Vir (Vir&lt;Vid) by the difference in gm between the read cell 12 and dummy cell 15.
The discharge starts, and the potentials of the input terminals of the flip-flop circuit 18 reach the sense level of the flip-flop circuit 18 with Vir higher than Vid (Vir&gt;Vid) by the difference in gm between the read cell 12 and dummy cell 15 (gm of read cell&gt;gm of dummy cell), though actually Vid has to be higher than Vir (Vir&lt;Vid), resulting in malfunction in which readout data DOUT of an on-state cell is output as that of an off-state cell.
As described above, since the conventional precharge/discharge nonvolatile memory circuit is not so designed as to have a sufficiently long precharge period, an imbalance is caused between the precharge levels of potentials on the read-cell and dummy-cell sides, and the precharge period is changed to the discharge period in the unbalanced state. For this reason, the precharge levels reach the sense level in reverse order, and the flip-flop circuit does not read out normal data.